Suspend-to-disk doesn't work anymore

[Natasha Kerensikova]

Synopsis: Suspend-to-disk doesn't work anymore
Category: <PR category (one line)>

System : OpenBSD 6.1
Details : OpenBSD 6.1-current (GENERIC.MP) #6: Fri May 12 15:12:39 CEST 2017
***@apollo.obspm.bsdfrog.org:/data/semarie/repos/openbsd/src/sys/arch/amd64/compile/GENERIC.MP

Architecture: OpenBSD.amd64
Machine : amd64
On my Thinkpad X220 (with Core i5) with full disk encryption,
OpenBSD doesn't resume after suspend to disk since my latest snanpshot
update (May 7th snapshot). Keeping the same userland and using kernels
helpfully provided by semarie, we bisected the problem to the commits
detailed below.
Suspend-to-disk a live OpenBSD. On next boot, it should resume from
disk, but instead it starts a standard boot with dirty filesystems.
Reverting the commits identified on github mirror by the hashes
d223d7cb85c1f2f705da547a0134b949655abe6a ("Switch glxsb(4), VIA
padlock and AES-NI drivers over to the new AES") and
cb3087542b323ec5bf5db9dc64f0d54dc40cca40 ("Switch OCF and IPsec over
to the new AES") fixes the problem, at least until commit
50f8ee3e5db5b40ae9a05db4742b05e8d975573d (May 11th).

dmesg:
OpenBSD 6.1-current (GENERIC.MP) #6: Fri May 12 15:12:39 CEST 2017
***@apollo.obspm.bsdfrog.org:/data/semarie/repos/openbsd/src/sys/arch/amd64/compile/GENERIC.MP
real mem = 4156157952 (3963MB)
avail mem = 4024406016 (3837MB)
mpath0 at root
scsibus0 at mpath0: 256 targets
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 2.6 @ 0xdae9c000 (65 entries)
bios0: vendor LENOVO version "8DET58WW (1.28 )" date 02/14/2012
bios0: LENOVO 4287CTO
acpi0 at bios0: rev 2
acpi0: sleep states S0 S3 S4 S5
acpi0: tables DSDT FACP SLIC SSDT SSDT SSDT HPET APIC MCFG ECDT ASF! TCPA SSDT SSDT UEFI UEFI UEFI
acpi0: wakeup devices LID_(S3) SLPB(S3) IGBE(S4) EXP4(S4) EXP7(S4) EHC1(S3) EHC2(S3) HDEF(S4)
acpitimer0 at acpi0: 3579545 Hz, 24 bits
acpihpet0 at acpi0: 14318179 Hz
acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz, 2492.29 MHz
cpu0: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,POPCNT,DEADLINE,AES,XSAVE,AVX,NXE,RDTSCP,LONG,LAHF,PERF,ITSC,SENSOR,ARAT
cpu0: 256KB 64b/line 8-way L2 cache
cpu0: TSC frequency 2492293840 Hz
cpu0: smt 0, core 0, package 0
mtrr: Pentium Pro MTRR support, 10 var ranges, 88 fixed ranges
cpu0: apic clock running at 99MHz
cpu0: mwait min=64, max=64, C-substates=0.2.1.1.2, IBE
cpu1 at mainbus0: apid 1 (application processor)
cpu1: Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz, 2491.91 MHz
cpu1: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,POPCNT,DEADLINE,AES,XSAVE,AVX,NXE,RDTSCP,LONG,LAHF,PERF,ITSC,SENSOR,ARAT
cpu1: 256KB 64b/line 8-way L2 cache
cpu1: smt 1, core 0, package 0
cpu2 at mainbus0: apid 2 (application processor)
cpu2: Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz, 2491.91 MHz
cpu2: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,POPCNT,DEADLINE,AES,XSAVE,AVX,NXE,RDTSCP,LONG,LAHF,PERF,ITSC,SENSOR,ARAT
cpu2: 256KB 64b/line 8-way L2 cache
cpu2: smt 0, core 1, package 0
cpu3 at mainbus0: apid 3 (application processor)
cpu3: Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz, 2491.91 MHz
cpu3: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,POPCNT,DEADLINE,AES,XSAVE,AVX,NXE,RDTSCP,LONG,LAHF,PERF,ITSC,SENSOR,ARAT
cpu3: 256KB 64b/line 8-way L2 cache
cpu3: smt 1, core 1, package 0
ioapic0 at mainbus0: apid 2 pa 0xfec00000, version 20, 24 pins
acpimcfg0 at acpi0 addr 0xf8000000, bus 0-63
acpiec0 at acpi0
acpiprt0 at acpi0: bus 0 (PCI0)
acpiprt1 at acpi0: bus -1 (PEG_)
acpiprt2 at acpi0: bus 2 (EXP1)
acpiprt3 at acpi0: bus 3 (EXP2)
acpiprt4 at acpi0: bus 5 (EXP4)
acpiprt5 at acpi0: bus 13 (EXP5)
acpiprt6 at acpi0: bus -1 (EXP7)
acpicpu0 at acpi0: C3(***@104 ***@0x415), C1(***@1 halt), PSS
acpicpu1 at acpi0: C3(***@104 ***@0x415), C1(***@1 halt), PSS
acpicpu2 at acpi0: C3(***@104 ***@0x415), C1(***@1 halt), PSS
acpicpu3 at acpi0: C3(***@104 ***@0x415), C1(***@1 halt), PSS
acpipwrres0 at acpi0: PUBS, resource for EHC1, EHC2
acpitz0 at acpi0: critical temperature is 99 degC
acpibtn0 at acpi0: LID_
acpibtn1 at acpi0: SLPB
"PNP0303" at acpi0 not configured
"LEN0020" at acpi0 not configured
"SMO1200" at acpi0 not configured
acpibat0 at acpi0: BAT0 model "42T4861" serial 12194 type LION oem "SANYO"
acpiac0 at acpi0: AC unit online
acpithinkpad0 at acpi0
"PNP0C14" at acpi0 not configured
"PNP0C14" at acpi0 not configured
acpidock0 at acpi0: GDCK not docked (0)
acpivideo0 at acpi0: VID_
acpivout at acpivideo0 not configured
acpivideo1 at acpi0: VID_
cpu0: Enhanced SpeedStep 2492 MHz: speeds: 2501, 2500, 2200, 2000, 1800, 1600, 1400, 1200, 1000, 800 MHz
pci0 at mainbus0 bus 0
pchb0 at pci0 dev 0 function 0 "Intel Core 2G Host" rev 0x09
inteldrm0 at pci0 dev 2 function 0 "Intel HD Graphics 3000" rev 0x09
drm0 at inteldrm0
inteldrm0: msi
inteldrm0: 1366x768, 32bpp
wsdisplay0 at inteldrm0 mux 1: console (std, vt100 emulation)
wsdisplay0: screen 1-5 added (std, vt100 emulation)
"Intel 6 Series MEI" rev 0x04 at pci0 dev 22 function 0 not configured
em0 at pci0 dev 25 function 0 "Intel 82579LM" rev 0x04: msi, address f0:de:f1:f3:16:ab
ehci0 at pci0 dev 26 function 0 "Intel 6 Series USB" rev 0x04: apic 2 int 16
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 configuration 1 interface 0 "Intel EHCI root hub" rev 2.00/1.00 addr 1
azalia0 at pci0 dev 27 function 0 "Intel 6 Series HD Audio" rev 0x04: msi
azalia0: codecs: Conexant CX20590, Intel/0x2805, using Conexant CX20590
audio0 at azalia0
ppb0 at pci0 dev 28 function 0 "Intel 6 Series PCIE" rev 0xb4: msi
pci1 at ppb0 bus 2
ppb1 at pci0 dev 28 function 1 "Intel 6 Series PCIE" rev 0xb4: msi
pci2 at ppb1 bus 3
iwn0 at pci2 dev 0 function 0 "Intel WiFi Link 1000" rev 0x00: msi, MIMO 1T2R, BGS, address 74:e5:0b:f3:73:8a
ppb2 at pci0 dev 28 function 3 "Intel 6 Series PCIE" rev 0xb4: msi
pci3 at ppb2 bus 5
ppb3 at pci0 dev 28 function 4 "Intel 6 Series PCIE" rev 0xb4: msi
pci4 at ppb3 bus 13
sdhc0 at pci4 dev 0 function 0 "Ricoh 5U822 SD/MMC" rev 0x07: apic 2 int 16
sdhc0: SDHC 3.0, 50 MHz base clock
sdmmc0 at sdhc0: 4-bit, sd high-speed, mmc high-speed, dma
ehci1 at pci0 dev 29 function 0 "Intel 6 Series USB" rev 0x04: apic 2 int 23
usb1 at ehci1: USB revision 2.0
uhub1 at usb1 configuration 1 interface 0 "Intel EHCI root hub" rev 2.00/1.00 addr 1
pcib0 at pci0 dev 31 function 0 "Intel QM67 LPC" rev 0x04
ahci0 at pci0 dev 31 function 2 "Intel 6 Series AHCI" rev 0x04: msi, AHCI 1.3
ahci0: port 0: 6.0Gb/s
scsibus1 at ahci0: 32 targets
sd0 at scsibus1 targ 0 lun 0: <ATA, ST1000LM035-1RK1, SDM1> SCSI3 0/direct fixed naa.5000c5009cd96696
sd0: 953869MB, 512 bytes/sector, 1953525168 sectors
ichiic0 at pci0 dev 31 function 3 "Intel 6 Series SMBus" rev 0x04: apic 2 int 18
iic0 at ichiic0
spdmem0 at iic0 addr 0x50: 4GB DDR3 SDRAM PC3-10600 SO-DIMM
isa0 at pcib0
isadma0 at isa0
pckbc0 at isa0 port 0x60/5 irq 1 irq 12
pckbd0 at pckbc0 (kbd slot)
wskbd0 at pckbd0: console keyboard, using wsdisplay0
pms0 at pckbc0 (aux slot)
wsmouse0 at pms0 mux 0
pcppi0 at isa0 port 0x61
spkr0 at pcppi0
aps0 at isa0 port 0x1600/31
uhub2 at uhub0 port 1 configuration 1 interface 0 "Intel Rate Matching Hub" rev 2.00/0.00 addr 2
uhub3 at uhub1 port 1 configuration 1 interface 0 "Intel Rate Matching Hub" rev 2.00/0.00 addr 2
umodem0 at uhub3 port 4 configuration 1 interface 1 "Lenovo F5521gw" rev 2.00/0.00 addr 3
umodem0: data interface 2, has CM over data, has break
umodem0: status change notification available
ucom0 at umodem0
umodem1 at uhub3 port 4 configuration 1 interface 3 "Lenovo F5521gw" rev 2.00/0.00 addr 3
umodem1: data interface 4, has CM over data, has break
umodem1: status change notification available
ucom1 at umodem1
umodem2 at uhub3 port 4 configuration 1 interface 9 "Lenovo F5521gw" rev 2.00/0.00 addr 3
umodem2: data interface 10, has CM over data, has break
umodem2: status change notification available
ucom2 at umodem2
ugen0 at uhub3 port 4 configuration 1 "Lenovo F5521gw" rev 2.00/0.00 addr 3
vscsi0 at root
scsibus2 at vscsi0: 256 targets
softraid0 at root
scsibus3 at softraid0: 256 targets
sd1 at scsibus3 targ 1 lun 0: <OPENBSD, SR CRYPTO, 006> SCSI2 0/direct fixed
sd1: 953866MB, 512 bytes/sector, 1953519473 sectors
root on sd1a (63848a4fade4a944.a) swap on sd1b dump on sd1b

usbdevs:
Controller /dev/usb0:
addr 1: high speed, self powered, config 1, EHCI root hub(0x0000), Intel(0x8086), rev 1.00
port 1 addr 2: high speed, self powered, config 1, Rate Matching Hub(0x0024), Intel(0x8087), rev 0.00
port 1 powered
port 2 powered
port 3 powered
port 4 powered
port 5 powered
port 6 powered
port 2 powered
port 3 powered
Controller /dev/usb1:
addr 1: high speed, self powered, config 1, EHCI root hub(0x0000), Intel(0x8086), rev 1.00
port 1 addr 2: high speed, self powered, config 1, Rate Matching Hub(0x0024), Intel(0x8087), rev 0.00
port 1 powered
port 2 powered
port 3 powered
port 4 addr 3: high speed, self powered, config 1, F5521gw(0x1911), Lenovo(0x0bdb), rev 0.00, iSerialNumber B9AE1BE8BAA3FBB0
port 5 powered
port 6 powered
port 7 powered
port 8 powered
port 2 powered
port 3 powered

pcidump:
Domain /dev/pci0:
0:0:0: Intel Core 2G Host
0x0000: Vendor ID: 8086 Product ID: 0104
0x0004: Command: 0006 Status: 0090
0x0008: Class: 06 Subclass: 00 Interface: 00 Revision: 09
0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 00
0x0010: BAR empty (00000000)
0x0014: BAR empty (00000000)
0x0018: BAR empty (00000000)
0x001c: BAR empty (00000000)
0x0020: BAR empty (00000000)
0x0024: BAR empty (00000000)
0x0028: Cardbus CIS: 00000000
0x002c: Subsystem Vendor ID: 17aa Product ID: 21da
0x0030: Expansion ROM Base Address: 00000000
0x0038: 00000000
0x003c: Interrupt Pin: 00 Line: 00 Min Gnt: 00 Max Lat: 00
0x00e0: Capability 0x09: Vendor Specific
0x0000: 01048086 00900006 06000009 00000000
0x0010: 00000000 00000000 00000000 00000000
0x0020: 00000000 00000000 00000000 21da17aa
0x0030: 00000000 000000e0 00000000 00000000
0x0040: fed19001 00000000 fed10001 00000000
0x0050: 00000211 00000011 00000000 db000001
0x0060: f8000005 00000000 fed18001 00000000
0x0070: fe000000 00000000 fe000c00 0000007f
0x0080: 11111110 00111111 0000001a 00000000
0x0090: 00000001 00000001 1e500001 00000001
0x00a0: 00000001 00000001 1e600001 00000001
0x00b0: dba00001 db800001 db000001 dfa00001
0x00c0: 00000000 00000000 00000000 00000000
0x00d0: 00000000 00000000 00000000 00000000
0x00e0: 010c0009 e200619e 14080090 00000000
0x00f0: 01000000 00000000 00060fb8 00000000
0:2:0: Intel HD Graphics 3000
0x0000: Vendor ID: 8086 Product ID: 0126
0x0004: Command: 0007 Status: 0090
0x0008: Class: 03 Subclass: 00 Interface: 00 Revision: 09
0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 00
0x0010: BAR mem 64bit addr: 0x00000000f0000000/0x00400000
0x0018: BAR mem prefetchable 64bit addr: 0x00000000e0000000/0x10000000
0x0020: BAR io addr: 0x00005000/0x0040
0x0024: BAR empty (00000000)
0x0028: Cardbus CIS: 00000000
0x002c: Subsystem Vendor ID: 17aa Product ID: 21da
0x0030: Expansion ROM Base Address: 00000000
0x0038: 00000000
0x003c: Interrupt Pin: 01 Line: 0b Min Gnt: 00 Max Lat: 00
0x0090: Capability 0x05: Message Signalled Interrupts (MSI)
0x00d0: Capability 0x01: Power Management
State: D0
0x00a4: Capability 0x13: PCI Advanced Features
0x0000: 01268086 00900007 03000009 00000000
0x0010: f0000004 00000000 e000000c 00000000
0x0020: 00005001 00000000 00000000 21da17aa
0x0030: 00000000 00000090 00000000 0000010b
0x0040: 010c0009 e200619e 14080090 00000000
0x0050: 00000211 00000011 00000000 dba00001
0x0060: 00020000 00000000 00000000 00000000
0x0070: 00000000 00000000 00000000 00000000
0x0080: 00000000 00000000 00000000 00000000
0x0090: 0001d005 fee00000 00000091 00000000
0x00a0: 00000000 03060013 00000000 00000000
0x00b0: 00000000 00000000 00000000 00000000
0x00c0: 00000000 00000000 00000000 00000000
0x00d0: 0022a401 00000000 00000000 00000000
0x00e0: 00000000 00000001 00008000 00000000
0x00f0: 00000000 00000000 00060000 daef6018
0:22:0: Intel 6 Series MEI
0x0000: Vendor ID: 8086 Product ID: 1c3a
0x0004: Command: 0006 Status: 0018
0x0008: Class: 07 Subclass: 80 Interface: 00 Revision: 04
0x000c: BIST: 00 Header Type: 80 Latency Timer: 00 Cache Line Size: 00
0x0010: BAR mem 64bit addr: 0x00000000f2525000/0x00000010
0x0018: BAR empty (00000000)
0x001c: BAR empty (00000000)
0x0020: BAR empty (00000000)
0x0024: BAR empty (00000000)
0x0028: Cardbus CIS: 00000000
0x002c: Subsystem Vendor ID: 17aa Product ID: 21da
0x0030: Expansion ROM Base Address: 00000000
0x0038: 00000000
0x003c: Interrupt Pin: 01 Line: 0b Min Gnt: 00 Max Lat: 00
0x0050: Capability 0x01: Power Management
State: D0
0x008c: Capability 0x05: Message Signalled Interrupts (MSI)
0x0000: 1c3a8086 00180006 07800004 00800000
0x0010: f2525004 00000000 00000000 00000000
0x0020: 00000000 00000000 00000000 21da17aa
0x0030: 00000000 00000050 00000000 0000010b
0x0040: 1e000245 80010020 60000006 10000fe0
0x0050: c8038c01 00000008 00000000 00000000
0x0060: 00000000 00000000 00000000 00000000
0x0070: 00000000 00000000 00000000 00000000
0x0080: 00000000 00000000 00000000 00800005
0x0090: 00000000 00000000 00000000 00000000
0x00a0: 00000000 00000000 00000000 00000000
0x00b0: 00000000 00000000 00000000 c0000002
0x00c0: cfd40b68 c177f476 768eebb2 681adde3
0x00d0: 5ee5e073 c3c76472 e455fb8c c6548da6
0x00e0: 00000000 00000000 00000000 00000000
0x00f0: 00000000 00000000 00000000 00000000
0:25:0: Intel 82579LM
0x0000: Vendor ID: 8086 Product ID: 1502
0x0004: Command: 0007 Status: 0010
0x0008: Class: 02 Subclass: 00 Interface: 00 Revision: 04
0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 00
0x0010: BAR mem 32bit addr: 0xf2500000/0x00020000
0x0014: BAR mem 32bit addr: 0xf252b000/0x00001000
0x0018: BAR io addr: 0x00005080/0x0020
0x001c: BAR empty (00000000)
0x0020: BAR empty (00000000)
0x0024: BAR empty (00000000)
0x0028: Cardbus CIS: 00000000
0x002c: Subsystem Vendor ID: 17aa Product ID: 21ce
0x0030: Expansion ROM Base Address: 00000000
0x0038: 00000000
0x003c: Interrupt Pin: 01 Line: 0a Min Gnt: 00 Max Lat: 00
0x00c8: Capability 0x01: Power Management
State: D0
0x00d0: Capability 0x05: Message Signalled Interrupts (MSI)
0x00e0: Capability 0x13: PCI Advanced Features
0x0000: 15028086 00100007 02000004 00000000
0x0010: f2500000 f252b000 00005081 00000000
0x0020: 00000000 00000000 00000000 21ce17aa
0x0030: 00000000 000000c8 00000000 0000010a
0x0040: 00000000 00000000 00000000 00000000
0x0050: 00000000 00000000 00000000 00000000
0x0060: 00000000 00000000 00000000 00000000
0x0070: 00000000 00000000 00000000 00000000
0x0080: 00000000 00000000 00000000 00000000
0x0090: 00000000 00000000 00000000 00000000
0x00a0: 00000000 00000000 00000000 00000000
0x00b0: 00000000 00000000 00000000 00000000
0x00c0: 00000000 00000000 c822d001 07002000
0x00d0: 0081e005 fee00000 00000000 00000072
0x00e0: 03060013 00000000 00000000 00000000
0x00f0: 00000000 00000000 00000000 00000000
0:26:0: Intel 6 Series USB
0x0000: Vendor ID: 8086 Product ID: 1c2d
0x0004: Command: 0006 Status: 0290
0x0008: Class: 0c Subclass: 03 Interface: 20 Revision: 04
0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 00
0x0010: BAR mem 32bit addr: 0xf252a000/0x00000400
0x0014: BAR empty (00000000)
0x0018: BAR empty (00000000)
0x001c: BAR empty (00000000)
0x0020: BAR empty (00000000)
0x0024: BAR empty (00000000)
0x0028: Cardbus CIS: 00000000
0x002c: Subsystem Vendor ID: 17aa Product ID: 21da
0x0030: Expansion ROM Base Address: 00000000
0x0038: 00000000
0x003c: Interrupt Pin: 01 Line: 0b Min Gnt: 00 Max Lat: 00
0x0050: Capability 0x01: Power Management
State: D0
0x0058: Capability 0x0a: Debug Port
0x0098: Capability 0x13: PCI Advanced Features
0x0000: 1c2d8086 02900006 0c032004 00000000
0x0010: f252a000 00000000 00000000 00000000
0x0020: 00000000 00000000 00000000 21da17aa
0x0030: 00000000 00000050 00000000 0000010b
0x0040: 00000000 00000000 00000000 00000000
0x0050: c9c25801 00000000 20a0980a 00000000
0x0060: 07a72020 00000000 00000001 c0082000
0x0070: 3fdf0000 00000000 00000000 00000000
0x0080: 00800000 930c8811 24000d30 00000000
0x0090: 00000000 00000000 03060013 00000000
0x00a0: 00000000 00000000 00000000 00000000
0x00b0: 00000000 00000000 00000000 00000000
0x00c0: 00000000 00000000 00000000 00000000
0x00d0: 00000000 00ffaa00 00000000 00000000
0x00e0: 00000000 00010080 40400000 1fff7004
0x00f0: 00000000 00808588 08060f87 205b1708
0:27:0: Intel 6 Series HD Audio
0x0000: Vendor ID: 8086 Product ID: 1c20
0x0004: Command: 0006 Status: 0010
0x0008: Class: 04 Subclass: 03 Interface: 00 Revision: 04
0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 10
0x0010: BAR mem 64bit addr: 0x00000000f2520000/0x00004000
0x0018: BAR empty (00000000)
0x001c: BAR empty (00000000)
0x0020: BAR empty (00000000)
0x0024: BAR empty (00000000)
0x0028: Cardbus CIS: 00000000
0x002c: Subsystem Vendor ID: 17aa Product ID: 21da
0x0030: Expansion ROM Base Address: 00000000
0x0038: 00000000
0x003c: Interrupt Pin: 01 Line: 07 Min Gnt: 00 Max Lat: 00
0x0050: Capability 0x01: Power Management
State: D0
0x0060: Capability 0x05: Message Signalled Interrupts (MSI)
0x0070: Capability 0x10: PCI Express
0x0100: Enhanced Capability 0x02: Virtual Channel Capability
0x0130: Enhanced Capability 0x05: Root Complex Link Declaration
0x0000: 1c208086 00100006 04030004 00000010
0x0010: f2520004 00000000 00000000 00000000
0x0020: 00000000 00000000 00000000 21da17aa
0x0030: 00000000 00000050 00000000 00000107
0x0040: 45000001 00000000 00000000 00000000
0x0050: c8426001 00000000 00000000 00000000
0x0060: 00817005 fee00000 00000000 000000b0
0x0070: 00910010 10000000 00100000 00000000
0x0080: 00000000 00000000 00000000 00000000
0x0090: 00000000 00000000 00000000 00000000
0x00a0: 00000000 00000000 00000000 00000000
0x00b0: 00000000 00000000 00000000 00000000
0x00c0: 01000400 40002402 82a30c00 02330010
0x00d0: 02a30c00 02330010 00000000 00000000
0x00e0: 00000000 00000000 00000000 00000000
0x00f0: 00000000 00000000 08060f87 00000000
0:28:0: Intel 6 Series PCIE
0x0000: Vendor ID: 8086 Product ID: 1c10
0x0004: Command: 0004 Status: 0010
0x0008: Class: 06 Subclass: 04 Interface: 00 Revision: b4
0x000c: BIST: 00 Header Type: 81 Latency Timer: 00 Cache Line Size: 10
0x0010: 00000000
0x0014: 00000000
0x0018: Primary Bus: 0 Secondary Bus: 2 Subordinate Bus: 2
Secondary Latency Timer: 00
0x001c: I/O Base: f0 I/O Limit: 00 Secondary Status: 0000
0x0020: Memory Base: fff0 Memory Limit: 0000
0x0024: Prefetch Memory Base: fff1 Prefetch Memory Limit: 0001
0x0028: Prefetch Memory Base Upper 32 Bits: 00000000
0x002c: Prefetch Memory Limit Upper 32 Bits: 00000000
0x0030: I/O Base Upper 16 Bits: 0000 I/O Limit Upper 16 Bits: 0000
0x0038: Expansion ROM Base Address: 00000000
0x003c: Interrupt Pin: 01 Line: 0b Bridge Control: 0000
0x0040: Capability 0x10: PCI Express
Link Speed: 2.5 / 5.0 GT/s Link Width: x0 / x1
0x0100: Enhanced Capability 0x00: Unknown
0x0080: Capability 0x05: Message Signalled Interrupts (MSI)
0x0090: Capability 0x0d: PCI-PCI
0x00a0: Capability 0x01: Power Management
State: D0
0x0000: 1c108086 00100004 060400b4 00810010
0x0010: 00000000 00000000 00020200 000000f0
0x0020: 0000fff0 0001fff1 00000000 00000000
0x0030: 00000000 00000040 00000000 0000010b
0x0040: 01428010 00008000 00100000 01124c12
0x0050: 10010003 0004b200 00000028 00000000
0x0060: 00000000 00000016 00000000 00000000
0x0070: 00010002 00000000 00000000 00000000
0x0080: 00019005 fee00000 00000061 00000000
0x0090: 0000a00d 21da17aa 00000000 00000000
0x00a0: c8020001 00000000 00000000 00000000
0x00b0: 00000000 00000000 00000000 00000000
0x00c0: 00000000 00000000 00000000 00000000
0x00d0: 01000000 00000b02 81118000 00000000
0x00e0: 00003f00 00000000 00000003 00000000
0x00f0: 00000000 00000000 08060f87 00000000
0:28:1: Intel 6 Series PCIE
0x0000: Vendor ID: 8086 Product ID: 1c12
0x0004: Command: 0007 Status: 0010
0x0008: Class: 06 Subclass: 04 Interface: 00 Revision: b4
0x000c: BIST: 00 Header Type: 81 Latency Timer: 00 Cache Line Size: 10
0x0010: 00000000
0x0014: 00000000
0x0018: Primary Bus: 0 Secondary Bus: 3 Subordinate Bus: 3
Secondary Latency Timer: 00
0x001c: I/O Base: f0 I/O Limit: 00 Secondary Status: 0000
0x0020: Memory Base: f240 Memory Limit: f240
0x0024: Prefetch Memory Base: fff1 Prefetch Memory Limit: 0001
0x0028: Prefetch Memory Base Upper 32 Bits: ffffffff
0x002c: Prefetch Memory Limit Upper 32 Bits: 00000000
0x0030: I/O Base Upper 16 Bits: 0000 I/O Limit Upper 16 Bits: 0000
0x0038: Expansion ROM Base Address: 00000000
0x003c: Interrupt Pin: 02 Line: 07 Bridge Control: 0000
0x0040: Capability 0x10: PCI Express
Link Speed: 2.5 / 5.0 GT/s Link Width: x1 / x1
0x0100: Enhanced Capability 0x00: Unknown
0x0080: Capability 0x05: Message Signalled Interrupts (MSI)
0x0090: Capability 0x0d: PCI-PCI
0x00a0: Capability 0x01: Power Management
State: D0
0x0000: 1c128086 00100007 060400b4 00810010
0x0010: 00000000 00000000 00030300 000000f0
0x0020: f240f240 0001fff1 ffffffff 00000000
0x0030: 00000000 00000040 00000000 00000207
0x0040: 01428010 00008000 00100000 02123c12
0x0050: 70110042 000cb200 00400028 00000000
0x0060: 00000000 00000016 00000000 00000000
0x0070: 00010002 00000000 00000000 00000000
0x0080: 00019005 fee00000 00000062 00000000
0x0090: 0000a00d 21da17aa 00000000 00000000
0x00a0: c8020001 00000000 00000000 00000000
0x00b0: 00000000 00000000 00000000 00000000
0x00c0: 00000000 00000000 00000000 00000000
0x00d0: 01000000 00000b02 81118000 00000000
0x00e0: 00000300 00000000 00000001 00000000
0x00f0: 00000000 00000000 08060f87 00000000
0:28:3: Intel 6 Series PCIE
0x0000: Vendor ID: 8086 Product ID: 1c16
0x0004: Command: 0007 Status: 0010
0x0008: Class: 06 Subclass: 04 Interface: 00 Revision: b4
0x000c: BIST: 00 Header Type: 81 Latency Timer: 00 Cache Line Size: 10
0x0010: 00000000
0x0014: 00000000
0x0018: Primary Bus: 0 Secondary Bus: 5 Subordinate Bus: 12
Secondary Latency Timer: 00
0x001c: I/O Base: 40 I/O Limit: 40 Secondary Status: 0000
0x0020: Memory Base: f1c0 Memory Limit: f230
0x0024: Prefetch Memory Base: f041 Prefetch Memory Limit: f0b1
0x0028: Prefetch Memory Base Upper 32 Bits: 00000000
0x002c: Prefetch Memory Limit Upper 32 Bits: 00000000
0x0030: I/O Base Upper 16 Bits: 0000 I/O Limit Upper 16 Bits: 0000
0x0038: Expansion ROM Base Address: 00000000
0x003c: Interrupt Pin: 04 Line: 0b Bridge Control: 0000
0x0040: Capability 0x10: PCI Express
Link Speed: 2.5 / 5.0 GT/s Link Width: x0 / x1
0x0100: Enhanced Capability 0x00: Unknown
0x0080: Capability 0x05: Message Signalled Interrupts (MSI)
0x0090: Capability 0x0d: PCI-PCI
0x00a0: Capability 0x01: Power Management
State: D0
0x0000: 1c168086 00100007 060400b4 00810010
0x0010: 00000000 00000000 000c0500 00004040
0x0020: f230f1c0 f0b1f041 00000000 00000000
0x0030: 00000000 00000040 00000000 0000040b
0x0040: 01428010 00008000 00100000 04124c12
0x0050: 10010003 001cb260 00000028 00000000
0x0060: 00000000 00000016 00000000 00000000
0x0070: 00010002 00000000 00000000 00000000
0x0080: 00019005 fee00000 00000063 00000000
0x0090: 0000a00d 21da17aa 00000000 00000000
0x00a0: c8020001 00000000 00000000 00000000
0x00b0: 00000000 00000000 00000000 00000000
0x00c0: 00000000 00000000 00000000 00000000
0x00d0: 01000000 00000b02 c1118002 00000000
0x00e0: 00000300 00000000 00000003 00000000
0x00f0: 00000000 00000000 08060f87 00000000
0:28:4: Intel 6 Series PCIE
0x0000: Vendor ID: 8086 Product ID: 1c18
0x0004: Command: 0007 Status: 0010
0x0008: Class: 06 Subclass: 04 Interface: 00 Revision: b4
0x000c: BIST: 00 Header Type: 81 Latency Timer: 00 Cache Line Size: 10
0x0010: 00000000
0x0014: 00000000
0x0018: Primary Bus: 0 Secondary Bus: 13 Subordinate Bus: 13
Secondary Latency Timer: 00
0x001c: I/O Base: 30 I/O Limit: 30 Secondary Status: 0000
0x0020: Memory Base: f140 Memory Limit: f1b0
0x0024: Prefetch Memory Base: f0c1 Prefetch Memory Limit: f131
0x0028: Prefetch Memory Base Upper 32 Bits: 00000000
0x002c: Prefetch Memory Limit Upper 32 Bits: 00000000
0x0030: I/O Base Upper 16 Bits: 0000 I/O Limit Upper 16 Bits: 0000
0x0038: Expansion ROM Base Address: 00000000
0x003c: Interrupt Pin: 01 Line: 0b Bridge Control: 0000
0x0040: Capability 0x10: PCI Express
Link Speed: 2.5 / 5.0 GT/s Link Width: x1 / x1
0x0100: Enhanced Capability 0x00: Unknown
0x0080: Capability 0x05: Message Signalled Interrupts (MSI)
0x0090: Capability 0x0d: PCI-PCI
0x00a0: Capability 0x01: Power Management
State: D0
0x0000: 1c188086 00100007 060400b4 00810010
0x0010: 00000000 00000000 000d0d00 00003030
0x0020: f1b0f140 f131f0c1 00000000 00000000
0x0030: 00000000 00000040 00000000 0000010b
0x0040: 01428010 00008000 00100000 05123c12
0x0050: 70110042 0024b260 00400028 00000000
0x0060: 00000000 00000016 00000000 00000000
0x0070: 00010002 00000000 00000000 00000000
0x0080: 00019005 fee00000 00000064 00000000
0x0090: 0000a00d 21da17aa 00000000 00000000
0x00a0: c8020001 00000000 00000000 00000000
0x00b0: 00000000 00000000 00000000 00000000
0x00c0: 00000000 00000000 00000000 00000000
0x00d0: 01000000 00000b02 c1118002 00000000
0x00e0: 00003f00 00000000 00000001 00000000
0x00f0: 00000000 00000000 08060f87 00000000
0:29:0: Intel 6 Series USB
0x0000: Vendor ID: 8086 Product ID: 1c26
0x0004: Command: 0006 Status: 0290
0x0008: Class: 0c Subclass: 03 Interface: 20 Revision: 04
0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 00
0x0010: BAR mem 32bit addr: 0xf2529000/0x00000400
0x0014: BAR empty (00000000)
0x0018: BAR empty (00000000)
0x001c: BAR empty (00000000)
0x0020: BAR empty (00000000)
0x0024: BAR empty (00000000)
0x0028: Cardbus CIS: 00000000
0x002c: Subsystem Vendor ID: 17aa Product ID: 21da
0x0030: Expansion ROM Base Address: 00000000
0x0038: 00000000
0x003c: Interrupt Pin: 01 Line: 0a Min Gnt: 00 Max Lat: 00
0x0050: Capability 0x01: Power Management
State: D0
0x0058: Capability 0x0a: Debug Port
0x0098: Capability 0x13: PCI Advanced Features
0x0000: 1c268086 02900006 0c032004 00000000
0x0010: f2529000 00000000 00000000 00000000
0x0020: 00000000 00000000 00000000 21da17aa
0x0030: 00000000 00000050 00000000 0000010a
0x0040: 00000000 00000000 00000000 00000000
0x0050: c9c25801 00000000 20a0980a 00000000
0x0060: 06472020 00000000 00000001 c0082000
0x0070: 3fdf0000 00000000 00000000 00000000
0x0080: 00800000 930c8811 24000d30 00000000
0x0090: 00000000 00000000 03060013 00000100
0x00a0: 00000000 00000000 00000000 00000000
0x00b0: 00000000 00000000 00000000 00000000
0x00c0: 00000000 00000000 00000000 00000000
0x00d0: 00000000 00ffaa00 00000000 00000000
0x00e0: 00000000 00000000 00000000 1ffdce04
0x00f0: 00000000 00808588 08060f87 205b1708
0:31:0: Intel QM67 LPC
0x0000: Vendor ID: 8086 Product ID: 1c4f
0x0004: Command: 0007 Status: 0210
0x0008: Class: 06 Subclass: 01 Interface: 00 Revision: 04
0x000c: BIST: 00 Header Type: 80 Latency Timer: 00 Cache Line Size: 00
0x0010: BAR empty (00000000)
0x0014: BAR empty (00000000)
0x0018: BAR empty (00000000)
0x001c: BAR empty (00000000)
0x0020: BAR empty (00000000)
0x0024: BAR empty (00000000)
0x0028: Cardbus CIS: 00000000
0x002c: Subsystem Vendor ID: 17aa Product ID: 21da
0x0030: Expansion ROM Base Address: 00000000
0x0038: 00000000
0x003c: Interrupt Pin: 00 Line: 00 Min Gnt: 00 Max Lat: 00
0x00e0: Capability 0x09: Vendor Specific
0x0000: 1c4f8086 02100007 06010004 00800000
0x0010: 00000000 00000000 00000000 00000000
0x0020: 00000000 00000000 00000000 21da17aa
0x0030: 00000000 000000e0 00000000 00000000
0x0040: 00000401 00000080 00000501 00000010
0x0050: 000000f8 00000000 00000000 00000000
0x0060: 0b0b070b 00000090 0a07800a 0000f0f8
0x0070: 00790078 007b007a 007d007c 007f007e
0x0080: 3f0f0010 007c1601 000c15e1 00000000
0x0090: 000c06a1 00000f00 00000000 00000000
0x00a0: 00800e04 00062939 00004700 80000000
0x00b0: 00000000 00000000 00020009 00000000
0x00c0: 00000000 00000000 00000000 00000000
0x00d0: 0000000f 00004567 0000ffc0 00000008
0x00e0: 100c0009 00000000 0e640293 00000000
0x00f0: fed1c001 00000000 08060f87 00000000
0:31:2: Intel 6 Series AHCI
0x0000: Vendor ID: 8086 Product ID: 1c03
0x0004: Command: 0007 Status: 02b0
0x0008: Class: 01 Subclass: 06 Interface: 01 Revision: 04
0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 00
0x0010: BAR io addr: 0x000050a8/0x0008
0x0014: BAR io addr: 0x000050bc/0x0004
0x0018: BAR io addr: 0x000050a0/0x0008
0x001c: BAR io addr: 0x000050b8/0x0004
0x0020: BAR io addr: 0x00005060/0x0020
0x0024: BAR mem 32bit addr: 0xf2528000/0x00000800
0x0028: Cardbus CIS: 00000000
0x002c: Subsystem Vendor ID: 17aa Product ID: 21da
0x0030: Expansion ROM Base Address: 00000000
0x0038: 00000000
0x003c: Interrupt Pin: 02 Line: 0b Min Gnt: 00 Max Lat: 00
0x0080: Capability 0x05: Message Signalled Interrupts (MSI)
0x0070: Capability 0x01: Power Management
State: D0
0x00a8: Capability 0x12: SATA
0x00b0: Capability 0x13: PCI Advanced Features
0x0000: 1c038086 02b00007 01060104 00000000
0x0010: 000050a9 000050bd 000050a1 000050b9
0x0020: 00005061 f2528000 00000000 21da17aa
0x0030: 00000000 00000080 00000000 0000020b
0x0040: 80008000 00000000 00000000 00000000
0x0050: 00000000 00000000 00000000 00000000
0x0060: 00000000 00000000 00000000 00000000
0x0070: 4003a801 00000008 00000000 00000000
0x0080: 00017005 fee00000 00000066 00000000
0x0090: 81132c60 2c000183 015c4208 00000000
0x00a0: 000000e0 00000039 0010b012 00000048
0x00b0: 03060013 00000000 00000000 00000000
0x00c0: 00000000 00000005 00000000 00000000
0x00d0: 00000000 00000000 00000000 00000000
0x00e0: 00000000 00000000 00000000 00000000
0x00f0: 00000000 00000000 08060f87 00000000
0:31:3: Intel 6 Series SMBus
0x0000: Vendor ID: 8086 Product ID: 1c22
0x0004: Command: 0003 Status: 0280
0x0008: Class: 0c Subclass: 05 Interface: 00 Revision: 04
0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 00
0x0010: BAR mem 64bit addr: 0x00000000f2524000/0x00000100
0x0018: BAR empty (00000000)
0x001c: BAR empty (00000000)
0x0020: BAR io addr: 0x0000efa0/0x0020
0x0024: BAR empty (00000000)
0x0028: Cardbus CIS: 00000000
0x002c: Subsystem Vendor ID: 17aa Product ID: 21da
0x0030: Expansion ROM Base Address: 00000000
0x0038: 00000000
0x003c: Interrupt Pin: 03 Line: 0b Min Gnt: 00 Max Lat: 00
0x0000: 1c228086 02800003 0c050004 00000000
0x0010: f2524004 00000000 00000000 00000000
0x0020: 0000efa1 00000000 00000000 21da17aa
0x0030: 00000000 00000000 00000000 0000030b
0x0040: 00000001 00000000 00000000 00000000
0x0050: 00000000 00000000 00000000 00000000
0x0060: 00040403 08080000 00000000 00000000
0x0070: 00000000 00000000 00000000 00000000
0x0080: 00000004 00000000 00000000 00000000
0x0090: 00000000 00000000 00000000 00000000
0x00a0: 00000000 00000000 00000000 00000000
0x00b0: 00000000 00000000 00000000 00000000
0x00c0: 00000000 00000000 00000000 00000000
0x00d0: 00000000 00000000 00000000 00000000
0x00e0: 00000000 00000000 00000000 00000000
0x00f0: 00000000 00000000 08060f87 00000000
3:0:0: Intel WiFi Link 1000
0x0000: Vendor ID: 8086 Product ID: 0084
0x0004: Command: 0006 Status: 0010
0x0008: Class: 02 Subclass: 80 Interface: 00 Revision: 00
0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size: 10
0x0010: BAR mem 64bit addr: 0x00000000f2400000/0x00002000
0x0018: BAR empty (00000000)
0x001c: BAR empty (00000000)
0x0020: BAR empty (00000000)
0x0024: BAR empty (00000000)
0x0028: Cardbus CIS: 00000000
0x002c: Subsystem Vendor ID: 8086 Product ID: 1315
0x0030: Expansion ROM Base Address: 00000000
0x0038: 00000000
0x003c: Interrupt Pin: 01 Line: 07 Min Gnt: 00 Max Lat: 00
0x00c8: Capability 0x01: Power Management
State: D0
0x00d0: Capability 0x05: Message Signalled Interrupts (MSI)
0x00e0: Capability 0x10: PCI Express
Link Speed: 2.5 / 2.5 GT/s Link Width: x1 / x1
0x0100: Enhanced Capability 0x01: Advanced Error Reporting
0x0140: Enhanced Capability 0x03: Device Serial Number
0x0000: 00848086 00100006 02800000 00000010
0x0010: f2400004 00000000 00000000 00000000
0x0020: 00000000 00000000 00000000 13158086
0x0030: 00000000 000000c8 00000000 00000107
0x0040: 00000000 00000000 00000000 00000000
0x0050: 00000000 00000000 00000000 00000000
0x0060: 00000000 00000000 00000000 00000000
0x0070: 00000000 00000000 00000000 00000000
0x0080: 00000000 00000000 00000000 00000000
0x0090: 00000000 00000000 00000000 00000000
0x00a0: 00000000 00000000 00000000 00000000
0x00b0: 00000000 00000000 00000000 00000000
0x00c0: 00000000 00000000 c823d001 0d000000
0x00d0: 0081e005 fee00000 00000000 00000073
0x00e0: 00010010 10008ec0 00190810 00069c11
0x00f0: 10110142 00000000 00000000 00000000
13:0:0: Ricoh 5U822 SD/MMC
0x0000: Vendor ID: 1180 Product ID: e822
0x0004: Command: 0006 Status: 0010
0x0008: Class: 08 Subclass: 80 Interface: 01 Revision: 07
0x000c: BIST: 00 Header Type: 80 Latency Timer: 00 Cache Line Size: 10
0x0010: BAR mem 32bit addr: 0xf1400000/0x00000100
0x0014: BAR empty (00000000)
0x0018: BAR empty (00000000)
0x001c: BAR empty (00000000)
0x0020: BAR empty (00000000)
0x0024: BAR empty (00000000)
0x0028: Cardbus CIS: 00000000
0x002c: Subsystem Vendor ID: 17aa Product ID: 21da
0x0030: Expansion ROM Base Address: 00000000
0x0038: 00000000
0x003c: Interrupt Pin: 01 Line: 0b Min Gnt: 00 Max Lat: 00
0x0050: Capability 0x05: Message Signalled Interrupts (MSI)
0x0078: Capability 0x01: Power Management
State: D0
0x0080: Capability 0x10: PCI Express
Link Speed: 2.5 / 2.5 GT/s Link Width: x1 / x1
0x0100: Enhanced Capability 0x02: Virtual Channel Capability
0x0800: Enhanced Capability 0x01: Advanced Error Reporting
0x0000: e8221180 00100006 08800107 00800010
0x0010: f1400000 00000000 00000000 00000000
0x0020: 00000000 00000000 00000000 21da17aa
0x0030: 00000000 00000050 00000000 0000010b
0x0040: 00000000 01826160 00000000 00000000
0x0050: 00807805 00000000 00000000 00000000
0x0060: 00000000 00000000 00007811 00000000
0x0070: 00000001 00000000 fe038001 48004000
0x0080: 00010010 0590ffc0 00092810 0107ec11
0x0090: 10110142 00000000 000003c0 00000000
0x00a0: 00000000 00000000 00000000 21da17aa
0x00b0: 00000004 00000000 00000000 000000a0
0x00c0: 00003000 00000000 87000000 00009800
0x00d0: 00000000 00004020 00000033 d9110020
0x00e0: 21e832b2 00008073 00000040 00000000
0x00f0: 00fe0030 00000000 02000018 00020000

acpidump:
begin-base64 644 APIC.8
QVBJQ5gAAAABskxFTk9WT1RQLThEICAggBIAAFBUTCACAAAAAADg/gEAAAAACAEAAQAAAAAIAgEB
AAAAAAgDAgEAAAAACAQDAQAAAAAIBQAAAAAAAAgGAAAAAAAACAcAAAAAAAAICAAAAAAAAQwCAAAA
wP4AAAAAAgoAAAIAAAAAAAIKAAkJAAAADQAEBgAFAAEEBgEFAAE=
====
begin-base64 644 APIC.dsl
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====
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====

[Sebastien Marie]

Post by Natasha Kerensikova

Synopsis: Suspend-to-disk doesn't work anymore
Category: <PR category (one line)>

System : OpenBSD 6.1
Details : OpenBSD 6.1-current (GENERIC.MP) #6: Fri May 12 15:12:39 CEST 2017
Architecture: OpenBSD.amd64
Machine : amd64
On my Thinkpad X220 (with Core i5) with full disk encryption,
OpenBSD doesn't resume after suspend to disk since my latest snanpshot
update (May 7th snapshot). Keeping the same userland and using kernels
helpfully provided by semarie, we bisected the problem to the commits
detailed below.
Suspend-to-disk a live OpenBSD. On next boot, it should resume from
disk, but instead it starts a standard boot with dirty filesystems.
Reverting the commits identified on github mirror by the hashes
d223d7cb85c1f2f705da547a0134b949655abe6a ("Switch glxsb(4), VIA
padlock and AES-NI drivers over to the new AES") and
cb3087542b323ec5bf5db9dc64f0d54dc40cca40 ("Switch OCF and IPsec over
to the new AES") fixes the problem, at least until commit
50f8ee3e5db5b40ae9a05db4742b05e8d975573d (May 11th).

With Natacha, we continued a bit a try to debug the problem.

By activating HIB_DEBUG, the resume showed that it failed due to wrong magic number:

[...]
sd1 at scsibus3 targ 1 lun 0: <OPENBSD, SR CRYPTO, 006> SCSI2 0/direct fixed
sd1: 953866MB, 512 bytes/sector, 1953519473 sectors
root on sd1a (63848a4fade4a944.a) swap on sd1b dump on sd1b
reading hibernate signature block location: 8641783
wrong magic number in hibernate signature: e82daa08

I am unsure the reason: it could be the hibernate part that don't write
it correctly or the resume part that don't read it correctly ? I dunno.

By "correctly" I mean: wrong aes key ? use of uninitialised or garbaged
struct ? Something that results a "bad state" on writing or reading.


With the last commit to revert AES_XTS to rijndael, I pushed it on
top of the tested tree (7 days old). The hibernate/resume works again.

It makes it to confirm the problem is related to the switch to
constant-time-aes in the context of full-disk-encryption.

Regarding the problem itself, I don't know enough the crypto part and
the initialisation code path to figure the reason. Does aes.c has some
initialisation that would arrive later than rijndael.c ? resulting a
first read on disk with wrong key or uninitialised structure ? I dunno.
I just hope this problem doesn't hide a more subtile underlined problem.

I expect the problem to be fixed in next snapshot (a one including the revert
of AES_XTS to rijndael).

Thanks.

[Mike Belopuhov]

Post by Sebastien Marie

Post by Natasha Kerensikova

Synopsis: Suspend-to-disk doesn't work anymore
Category: <PR category (one line)>

System : OpenBSD 6.1
Details : OpenBSD 6.1-current (GENERIC.MP) #6: Fri May 12 15:12:39 CEST 2017
Architecture: OpenBSD.amd64
Machine : amd64
On my Thinkpad X220 (with Core i5) with full disk encryption,
OpenBSD doesn't resume after suspend to disk since my latest snanpshot
update (May 7th snapshot). Keeping the same userland and using kernels
helpfully provided by semarie, we bisected the problem to the commits
detailed below.
Suspend-to-disk a live OpenBSD. On next boot, it should resume from
disk, but instead it starts a standard boot with dirty filesystems.
Reverting the commits identified on github mirror by the hashes
d223d7cb85c1f2f705da547a0134b949655abe6a ("Switch glxsb(4), VIA
padlock and AES-NI drivers over to the new AES") and
cb3087542b323ec5bf5db9dc64f0d54dc40cca40 ("Switch OCF and IPsec over
to the new AES") fixes the problem, at least until commit
50f8ee3e5db5b40ae9a05db4742b05e8d975573d (May 11th).

With Natacha, we continued a bit a try to debug the problem.

Thank you for a follow up mail. If you can find more info,
this would be helpful.

Post by Sebastien Marie
[...]
sd1 at scsibus3 targ 1 lun 0: <OPENBSD, SR CRYPTO, 006> SCSI2 0/direct fixed
sd1: 953866MB, 512 bytes/sector, 1953519473 sectors
root on sd1a (63848a4fade4a944.a) swap on sd1b dump on sd1b
reading hibernate signature block location: 8641783
wrong magic number in hibernate signature: e82daa08
I am unsure the reason: it could be the hibernate part that don't write
it correctly or the resume part that don't read it correctly ? I dunno.
By "correctly" I mean: wrong aes key ? use of uninitialised or garbaged
struct ? Something that results a "bad state" on writing or reading.
With the last commit to revert AES_XTS to rijndael, I pushed it on
top of the tested tree (7 days old). The hibernate/resume works again.
It makes it to confirm the problem is related to the switch to
constant-time-aes in the context of full-disk-encryption.

Thanks for verifying this. I've looked through the sr_hibernate_io
(that's hib->io_func) but couldn't find anything wrong with it. The
only thing that springs to mind is that AES_CTX and therefore the
XTS context (aes_xts_ctx) is larger and requires more stack space.
Though I can't see what might be affected by that.

Post by Sebastien Marie
Regarding the problem itself, I don't know enough the crypto part and
the initialisation code path to figure the reason. Does aes.c has some
initialisation that would arrive later than rijndael.c ? resulting a
first read on disk with wrong key or uninitialised structure ? I dunno.

No. Otherwise we would see this kind of issues elsewhere.

Post by Sebastien Marie
I just hope this problem doesn't hide a more subtile underlined problem.

It probably does.

Post by Sebastien Marie
I expect the problem to be fixed in next snapshot (a one including the revert
of AES_XTS to rijndael).
Thanks.
--
Sebastien Marie

[Sebastien Marie]

Post by Mike Belopuhov

Post by Sebastien Marie
With the last commit to revert AES_XTS to rijndael, I pushed it on
top of the tested tree (7 days old). The hibernate/resume works again.
It makes it to confirm the problem is related to the switch to
constant-time-aes in the context of full-disk-encryption.

Thanks for verifying this. I've looked through the sr_hibernate_io
(that's hib->io_func) but couldn't find anything wrong with it. The
only thing that springs to mind is that AES_CTX and therefore the
XTS context (aes_xts_ctx) is larger and requires more stack space.
Though I can't see what might be affected by that.

I quickly check the difference of struct size and come back with some
idea to test.

- aes_xts_ctx based on AES_CTX has sizeof()=1464
- aes_xts_ctx based on rijndael_ctx has sizeof()=992


do you think just adding padding of 472 (1464-992) at end of `struct
aes_xts_ctx' (rijndael_ctx version) would be enough to test it ?

Something like:

diff --git a/sys/crypto/xform.c b/sys/crypto/xform.c
index 71e173b44..9775d030c 100644
--- a/sys/crypto/xform.c
+++ b/sys/crypto/xform.c
@@ -125,6 +125,7 @@ struct aes_xts_ctx {
rijndael_ctx key1;
rijndael_ctx key2;
u_int8_t tweak[AES_XTS_BLOCKSIZE];
+ u_int8_t _pad[472];
};

/* Helper */


if the hibernate/resume process is able to complete with the padded
version, we could exclude the struct size of the equation. and if the
process fail, it means the size matters.

any additional thing to do for testing padding (initialisation or
something else) ? you know better than me this subsystem :)

Thanks.

[Mike Belopuhov]

Post by Sebastien Marie

Post by Mike Belopuhov

Post by Sebastien Marie
With the last commit to revert AES_XTS to rijndael, I pushed it on
top of the tested tree (7 days old). The hibernate/resume works again.
It makes it to confirm the problem is related to the switch to
constant-time-aes in the context of full-disk-encryption.

Thanks for verifying this. I've looked through the sr_hibernate_io
(that's hib->io_func) but couldn't find anything wrong with it. The
only thing that springs to mind is that AES_CTX and therefore the
XTS context (aes_xts_ctx) is larger and requires more stack space.
Though I can't see what might be affected by that.

I quickly check the difference of struct size and come back with some
idea to test.
- aes_xts_ctx based on AES_CTX has sizeof()=1464
- aes_xts_ctx based on rijndael_ctx has sizeof()=992
do you think just adding padding of 472 (1464-992) at end of `struct
aes_xts_ctx' (rijndael_ctx version) would be enough to test it ?
diff --git a/sys/crypto/xform.c b/sys/crypto/xform.c
index 71e173b44..9775d030c 100644
--- a/sys/crypto/xform.c
+++ b/sys/crypto/xform.c
@@ -125,6 +125,7 @@ struct aes_xts_ctx {
rijndael_ctx key1;
rijndael_ctx key2;
u_int8_t tweak[AES_XTS_BLOCKSIZE];
+ u_int8_t _pad[472];
};
/* Helper */

Good question. I would try both in the end of the structure and in
the beginning, in attempt to at least rule out stack corruption.

Post by Sebastien Marie
if the hibernate/resume process is able to complete with the padded
version, we could exclude the struct size of the equation. and if the
process fail, it means the size matters.

I would agree with this.

Post by Sebastien Marie
any additional thing to do for testing padding (initialisation or
something else) ? you know better than me this subsystem :)

Nothing springs to mind, but I didn't have time to investigate
any further yet.

[Mike Larkin]

Post by Mike Belopuhov

Post by Sebastien Marie

Post by Mike Belopuhov

Post by Sebastien Marie
With the last commit to revert AES_XTS to rijndael, I pushed it on
top of the tested tree (7 days old). The hibernate/resume works again.
It makes it to confirm the problem is related to the switch to
constant-time-aes in the context of full-disk-encryption.

Thanks for verifying this. I've looked through the sr_hibernate_io
(that's hib->io_func) but couldn't find anything wrong with it. The
only thing that springs to mind is that AES_CTX and therefore the
XTS context (aes_xts_ctx) is larger and requires more stack space.
Though I can't see what might be affected by that.

I quickly check the difference of struct size and come back with some
idea to test.
- aes_xts_ctx based on AES_CTX has sizeof()=1464
- aes_xts_ctx based on rijndael_ctx has sizeof()=992
do you think just adding padding of 472 (1464-992) at end of `struct
aes_xts_ctx' (rijndael_ctx version) would be enough to test it ?
diff --git a/sys/crypto/xform.c b/sys/crypto/xform.c
index 71e173b44..9775d030c 100644
--- a/sys/crypto/xform.c
+++ b/sys/crypto/xform.c
@@ -125,6 +125,7 @@ struct aes_xts_ctx {
rijndael_ctx key1;
rijndael_ctx key2;
u_int8_t tweak[AES_XTS_BLOCKSIZE];
+ u_int8_t _pad[472];
};
/* Helper */

Good question. I would try both in the end of the structure and in
the beginning, in attempt to at least rule out stack corruption.

Post by Sebastien Marie
if the hibernate/resume process is able to complete with the padded
version, we could exclude the struct size of the equation. and if the
process fail, it means the size matters.

I would agree with this.

Post by Sebastien Marie
any additional thing to do for testing padding (initialisation or
something else) ? you know better than me this subsystem :)

Nothing springs to mind, but I didn't have time to investigate
any further yet.

Is the new AES implementation side effect free? It cannot touch any memory
outside the scratch page used by the sr crypto suspend routine.

-ml

[Mike Belopuhov]

Post by Mike Larkin

Post by Mike Belopuhov

Post by Sebastien Marie

Post by Mike Belopuhov

Post by Sebastien Marie
With the last commit to revert AES_XTS to rijndael, I pushed it on
top of the tested tree (7 days old). The hibernate/resume works again.
It makes it to confirm the problem is related to the switch to
constant-time-aes in the context of full-disk-encryption.

Thanks for verifying this. I've looked through the sr_hibernate_io
(that's hib->io_func) but couldn't find anything wrong with it. The
only thing that springs to mind is that AES_CTX and therefore the
XTS context (aes_xts_ctx) is larger and requires more stack space.
Though I can't see what might be affected by that.

I quickly check the difference of struct size and come back with some
idea to test.
- aes_xts_ctx based on AES_CTX has sizeof()=1464
- aes_xts_ctx based on rijndael_ctx has sizeof()=992
do you think just adding padding of 472 (1464-992) at end of `struct
aes_xts_ctx' (rijndael_ctx version) would be enough to test it ?
diff --git a/sys/crypto/xform.c b/sys/crypto/xform.c
index 71e173b44..9775d030c 100644
--- a/sys/crypto/xform.c
+++ b/sys/crypto/xform.c
@@ -125,6 +125,7 @@ struct aes_xts_ctx {
rijndael_ctx key1;
rijndael_ctx key2;
u_int8_t tweak[AES_XTS_BLOCKSIZE];
+ u_int8_t _pad[472];
};
/* Helper */

Good question. I would try both in the end of the structure and in
the beginning, in attempt to at least rule out stack corruption.

Post by Sebastien Marie
if the hibernate/resume process is able to complete with the padded
version, we could exclude the struct size of the equation. and if the
process fail, it means the size matters.

I would agree with this.

Post by Sebastien Marie
any additional thing to do for testing padding (initialisation or
something else) ? you know better than me this subsystem :)

Nothing springs to mind, but I didn't have time to investigate
any further yet.

Is the new AES implementation side effect free? It cannot touch any memory
outside the scratch page used by the sr crypto suspend routine.
-ml

It doesn't touch any memory except for its context which is on the stack.
If this stack must fit into the scratch page, I don't see any indication
of enforcing it or a comment explaining it. aes_xts_ctx is not part of
the "*my = page;" structure.

[Mike Larkin]

Post by Mike Belopuhov

Post by Mike Larkin

Post by Mike Belopuhov

Post by Sebastien Marie

Post by Mike Belopuhov

Post by Sebastien Marie
With the last commit to revert AES_XTS to rijndael, I pushed it on
top of the tested tree (7 days old). The hibernate/resume works again.
It makes it to confirm the problem is related to the switch to
constant-time-aes in the context of full-disk-encryption.

Thanks for verifying this. I've looked through the sr_hibernate_io
(that's hib->io_func) but couldn't find anything wrong with it. The
only thing that springs to mind is that AES_CTX and therefore the
XTS context (aes_xts_ctx) is larger and requires more stack space.
Though I can't see what might be affected by that.

I quickly check the difference of struct size and come back with some
idea to test.
- aes_xts_ctx based on AES_CTX has sizeof()=1464
- aes_xts_ctx based on rijndael_ctx has sizeof()=992
do you think just adding padding of 472 (1464-992) at end of `struct
aes_xts_ctx' (rijndael_ctx version) would be enough to test it ?
diff --git a/sys/crypto/xform.c b/sys/crypto/xform.c
index 71e173b44..9775d030c 100644
--- a/sys/crypto/xform.c
+++ b/sys/crypto/xform.c
@@ -125,6 +125,7 @@ struct aes_xts_ctx {
rijndael_ctx key1;
rijndael_ctx key2;
u_int8_t tweak[AES_XTS_BLOCKSIZE];
+ u_int8_t _pad[472];
};
/* Helper */

Good question. I would try both in the end of the structure and in
the beginning, in attempt to at least rule out stack corruption.

Post by Sebastien Marie
if the hibernate/resume process is able to complete with the padded
version, we could exclude the struct size of the equation. and if the
process fail, it means the size matters.

I would agree with this.

Post by Sebastien Marie
any additional thing to do for testing padding (initialisation or
something else) ? you know better than me this subsystem :)

Nothing springs to mind, but I didn't have time to investigate
any further yet.

Is the new AES implementation side effect free? It cannot touch any memory
outside the scratch page used by the sr crypto suspend routine.
-ml

It doesn't touch any memory except for its context which is on the stack.
If this stack must fit into the scratch page, I don't see any indication
of enforcing it or a comment explaining it. aes_xts_ctx is not part of
the "*my = page;" structure.

A private stack is in use while hibernate is occurring, so as long as the stack
doesn't grow past 3 pages it should be ok. The *my = page is for any extra
working area the I/O routines need.

-ml

[Sebastien Marie]

Post by Mike Belopuhov

Post by Sebastien Marie
It makes it to confirm the problem is related to the switch to
constant-time-aes in the context of full-disk-encryption.

Thanks for verifying this. I've looked through the sr_hibernate_io
(that's hib->io_func) but couldn't find anything wrong with it. The
only thing that springs to mind is that AES_CTX and therefore the
XTS context (aes_xts_ctx) is larger and requires more stack space.
Though I can't see what might be affected by that.

While looking at code source and `struct aes_xts_ctx` definition (in
order to add the padding stuff), I see the following:


1. `struct aes_xts_ctx` and aes_xts_* funtions are defined in
crypto/xform.c and used by regular kernel code.

with the constant-time AES (so the faulting one, before reverting), the
code was using AES_CTX and AES_*() functions.

crypto/xform.c:
123 struct aes_xts_ctx {
124 AES_CTX key1;
125 AES_CTX key2;
126 u_int8_t tweak[AES_XTS_BLOCKSIZE];
127 };

and later:
480 void
481 aes_xts_reinit(caddr_t key, u_int8_t *iv)
482 {
...
496 /* Last 64 bits of IV are always zero */
497 bzero(ctx->tweak + AES_XTS_IVSIZE, AES_XTS_IVSIZE);
498
499 AES_Encrypt(&ctx->key2, ctx->tweak, ctx->tweak);
500 }



2. `struct aes_xts_ctx` and functions are *also* defined in
lib/libsa/aes_xts.h and used by bootloader code. They are using
rijndael code.

Please note that the switch to AES_CTX does *not* touch them. There were
still use rijndael code and struct, while the kernel was using AES_CTX
version.

lib/libsa/aes_xts.h:
27 struct aes_xts_ctx {
28 rijndael_ctx key1;
29 rijndael_ctx key2;
30 u_int8_t tweak[AES_XTS_BLOCKSIZE];
31 };

lib/libsa/aes_xts.c:
25 void
26 aes_xts_reinit(struct aes_xts_ctx *ctx, u_int8_t *iv)
27 {
...
40 /* Last 64 bits of IV are always zero */
41 bzero(ctx->tweak + AES_XTS_IVSIZE, AES_XTS_IVSIZE);
42
43 rijndael_encrypt(&ctx->key2, ctx->tweak, ctx->tweak);
44 }



3. in dev/softraid.c, the hibernate code sr_hibernate_io() seems to use
to bootloader definition of `struct aes_xts_ctx`:

dev/softraid.c:
53 #ifdef HIBERNATE
54 #include <lib/libsa/aes_xts.h>
55 #include <sys/hibernate.h>
56 #include <scsi/sdvar.h>
57 #endif /* HIBERNATE */

but as it is a regular kernel code and not bootloader code, I expect the
linkage of aes_xts_*() functions to be done using kernel code (so
AES_* version).

The structure used was rijndael_ctx based (sizeof=992), and functions
used was AES_Encrypt() based. As AES_* functions operated on larger
struct (sizeof=1464), it was resulting some garbage and stack corruption
inside sr_hibernate_io().



As we move back to rijndael code for AES_XTS, bootloader code and kernel
code come back in sync, and sr_hibernate_io() uses right code now.

I see several possibles things to do to avoid future mistakes:

- in dev/softraid.c : doesn't use libsa code but standard kernel code.
But I dunno if it would be compatible or not. It depends if we share
some elements with bootloader or not.

- in crypto/xform.c and lib/libsa/aes_xts.h : add a comment to recall
that the struct should be keep in sync together.



Does this analyze makes sens ?